1. Field
The embodiments discussed herein are related to a successive approximation register analog to digital converter (ADC) and method of adjusting a delay thereof.
2. Description of Related Art
A successive approximation register (SAR) analog to digital converter (ADC) may include a simple circuit with high consistency with CMOS processes and may convert a signal at high-speed. The successive approximation register analog-to-digital converter includes a digital-to-analog converter (DAC), a comparator, and a DAC control circuit. As an entire operation, an input voltage during a sampling period is sampled and the sampled signal is stored as a sample voltage and the sample voltage and voltages to be compared are successively compared during a subsequent comparison period. Through successive comparison operations, the DAC generates a plurality of voltages to be compared based on a reference voltage Vref, which correspond to a stride of ½ Vref, ¼ Vref, ⅛ Vref . . . , and so on, according to digital codes from the DAC circuit. In one comparison operation, the comparator compares one voltage to be compared that corresponds to one digital code with the sample voltage and determines a magnitude relation between the voltage to be compared and the sample voltage. According to an output of a comparison result of the comparator, the DAC control circuit changes a digital code, thereby changing the voltage to be compared from a large stride to a small stride to successively perform comparison for N-times. An N bits digital code that corresponds to the sample voltage may be obtained through N-times successive comparisons. A magnitude relation between the sample voltage and a voltage to be compared is sufficient information for the comparator. For example, the DAC may generate a difference between the voltage to be compared and the sample voltage, and the comparator may compare the DAC output and a ground voltage.
A DAC of the successive approximation register analog-to-digital converter includes a capacitive DAC, or, a capacitive main DAC and a resistor sub DAC are used. During a sampling period, the capacitive DAC applies input voltages in parallel to a plurality of capacitance elements and each capacitance element is charged to a voltage value substantially equal to the input voltage. After the sampling, one end of the plurality of capacitance elements is selectively coupled, for example, to Vref or GND, and the other end is coupled to a common terminal by switching couplings of the plurality of the capacitance elements by a switch circuit. Electronic charges may be redistributed and a potential corresponding to the voltage obtained by dividing the capacitance between the Vref and GND and the input voltage appears at the common terminal. The potential which appears at the common terminal may be input to the comparator. A desired voltage to be compared is generated by controlling a coupling of the switch circuit using a digital code from the DAC control circuit.
In a synchronous successive approximation register analog-to-digital converter, a DAC, a comparator, and a DAC control circuit operate in synchronization with an external clock signal. The external clock signal may be faster than a clock signal for sampling.
In an asynchronous successive approximation Register analog-to-digital converter, an operation clock signal that corresponds to one pulse is generated from one comparison result output from the comparator based on a change in a comparator output signal. The DAC, the comparator, and the DAC control circuit are operated in synchronization with the clock signal. Since the output of the comparator may be input to the asynchronous successive approximation register analog-to-digital converter and an output of the asynchronous successive approximation register analog-to-digital converter may become a reset input to the comparator, a loop is formed, thereby a clock signal being generated through self-excitation. For example, a pulse signal that is generated based on the output of the comparator is delayed by a delay circuit and the delayed pulse signal may be input to a reset terminal of the comparator.
When the delay circuit includes a delay element array using a gate circuit such as an inverter, the delay quantity (e.g., the time delay) of the delay circuit may be varied depending on changes in fabrication processes, temperatures, and power supply voltages. When the change increases the delay quantity, one cycle of a self-excitation clock increases and a certain times of comparison operations (N times for N bit resolution) within a certain sampling cycle may not be executed. When a delay quantity decreases due to the change, one cycle of a self-excitation clock decreases and operations of the DAC, the comparator, and the DAC control circuit may not follow the clock speed.
In order to adjust variation in delays of the delay circuit, the successive approximation register analog-to-digital converter may use a phase locked loop (PLL) and a delay locked loop (DLL).